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never stop thinking. hys72d128300gbr-[5/6/7]-b hys72d256320gbr-[5/6/7]-b hys72d128500hr-[7f/7]-b hys72d128321gbr-[5/6/7]-b 184-pin registered double data rate sdram module reg dimm ddr sdram green product lead containing product data sheet, rev. 0.5, dec. 2003 memory products
edition 2003-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys72d128300gbr-[5/6/7]-b hys72d256320gbr-[5/6/7]-b hys72d128500hr-[7f/7]-b hys72d128321gbr-[5/6/7]-b 184-pin registered double data rate sdram module reg dimm data sheet, rev. 0.5, dec. 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm hys72d128300gbr-[5/6/7]-b, hys72d256320gbr-[5/6/7]-b, hys72d128500hr-[7f/7]-b revision history: rev. 0.5 2003-12 previous version: page subjects (major changes since last revision) we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module overview data sheet 6 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module overview data sheet 6 rev. 0.5, 2003-12 1overview 1.1 features ? 184-pin registered 8-byte dual-in-line ddr sdram module for ?1u? pc, workstation and server main memory applications one rank 128m 72 organization and two rank 256m 72 organization jedec standard double data rate synchronous drams (ddr sdram) with a single + 2.5 v ( 0.2 v) power supply and +2.6( 0.1 v) power supply for ddr400 built with ddr sdrams in 66-lead tsopii and fbga 60 package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible re-drive for all input signals using register and pll devices. serial presence detect with e 2 prom low profile modules form factor: 133.35 mm 28.58 mm (1.1?) 4.00 mm and 133.35 mm 30.48 mm (1.2?) 4.00 mm based on jedec standard reference card layout rawcard ?b?, ?c? and ?d? gold plated contacts 1.2 description the hys72d[128/256][300/320/321/500][gbr/hr]-[5/6/7/7f]-b are low profile versions of the standard registered dimm modules with 1.1? inch (28.58) and 1.2? inch (30,40 mm) height for 1u server applications. the low profile dimm versions are available as 128m 72 (1 gb) and 256m 72 (2 gb). the memory array is designed with double data rate synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycl e to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 1 performance part number speed code ? 5 ? 6 ? 7 ? 7f unit speed grade component ddr400b ddr333b ddr266a ddr266 ? module pc3200?3033 pc2700?2533 pc2100?2033 pc2100?2022 ? max. clock frequency @ cl = 3 f ck3 200 166 ? ? mhz @ cl = 2.5 f ck2.5 166 166 143 143 mhz @ cl = 2 f ck2 133 133 133 133 mhz
data sheet 7 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module overview data sheet 7 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module overview table 2 ordering information 1)2) type compliance code 2) description sdram technology pc3200 (cl=3) hys72d128300gbr?5?b pc3200r?30331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?5?b pc3200r?30331?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320gbr?5?b pc3200r?30331?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2700 (cl=2.5) hys72d128300gbr?6?b pc2700r?25330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?6?b pc2700r?25330?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320gbr?6?b pc2700r?25330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2100 (cl=2) hys72d128300gbr?7?b pc2100r?20330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?7?b pc2100r?20330?b0 two ranks1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320gbr?7?b pc2100r?20330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128500hr?7f?b pc2100r?20220?m one rank 1gbyte reg. ecc dimm 512 mbit ( 4) hys72d128500hr?7?b pc2100r?20330?m one rank 1gbyte reg. ecc dimm 512 mbit ( 4) 1) all part numbers end with a place code (not shown), designa ting the silicon-die revision. reference information available on request. example: hys72d128300gbr-[5/6/7]-b, indicating rev.b die are used for sdram components. 2) the compliance code is printed on the module labels and describes the speed sort for example ?pc2100r?, the latencies (for example ?20330? me ans cas latency = 2.5, t rcd latency = 3 and t rp latency =3 ) and the raw card used for this module
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 8 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 8 rev. 0.5, 2003-12 2 pin configuration table 3 pin definitions and functions symbol type function a0 - a11,a12 address inputs ba0, ba1 bank selects dq0 - dq63 data input/output cb0 - cb7 check bits ( 72 organization only) ras ,cas ,we command inputs cke0, cke1 clock enable dqs0 - dqs8 sdram low data strobes ck0, ck0 differential clock input dm0 - dm8 dqs9 - dqs17 sdram low data mask/ high data strobes s0 - s1 chip selects v dd power (+2.5 v) v ss ground v ddq i/o driver power supply v ddid vdd indentification flag v ddspd eeprom power supply v ref i/o reference supply scl serial bus clock sda serial bus data line sa0 - sa2 slave address select nc no connect du don?t use reset reset pin (forces register inputs low) 1) 1) for detailed description of the power up and power manag ement on ddr registered dimms see the application note at the end of this datasheet
data sheet 9 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 9 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module table 4 pin configuration 1) pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref 48 a0 94 dq4 141 a10 2 dq0 49 cb2 95 dq5 142 cb6 3 v ss 50 v ss 96 v ddq 143 v ddq 4 dq1 51 cb3 97 dqs9 144 cb7 5dqs052ba1 98dq6 key 6dq2 key 99 dq7 145 v ss 7 v dd 53 dq32 100 v ss 146 dq36 8dq3 54 v ddq 101 nc 147 dq37 9nc 55dq33102nc 148 v dd 10 reset 56 dqs4 103 nc 149 dm4/dqs13 11 v ss 57 dq34 104 v ddq 150 dq38 12 dq8 58 v ss 105 dq12 151 dq39 13 dq9 59 ba0 106 dq13 152 v ss 14 dqs1 60 dq35 107 dqs10 153 dq44 15 v ddq 61 dq40 108 v dd 154 ras 16 du 62 v ddq 109 dq14 155 dq45 17 du 63 we 110 dq15 156 v ddq 18 v ss 64 dq41 111 cke1 157 s0 19 dq10 65 cas 112 v ddq 158 s1 20 dq11 66 v ss 113 nc 159 dqs14 21 cke0 67 dqs5 114 dq20 160 v ss 22 v ddq 68 dq42 115 nc / a12 161 dq46 23 dq16 69 dq43 116 v ss 162 dq47 24 dq17 70 v dd 117 dq21 163 nc 25 dqs2 71 nc 118 a11 164 v ddq 26 v ss 72 dq48 119 dqs11 165 dq52 27 a9 73 dq49 120 v dd 166 dq53 28 dq18 74 v ss 121 dq22 167 nc 29 a7 75 du 122 a8 168 v dd 30 v ddq 76 du 123 dq23 169 dqs15 31 dq19 77 v ddq 124 v ss 170 dq54 32 a5 78 dqs6 125 a6 171 dq55 33 dq24 79 dq50 126 dq28 172 v ddq 34 v ss 80 dq51 127 dq29 173 nc 35 dq25 81 v ss 128 v ddq 174 dq60 36 dqs3 82 v ddid 129 dqs12 175 dq61 37 a4 83 dq56 130 a3 176 v ss 38 v dd 84 dq57 131 dq30 177 dqs16 39 dq26 85 v dd 132 v ss 178 dq62 40 dq27 86 dqs7 133 dq31 179 dq63 41 a2 87 dq58 134 cb4 180 v ddq
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 10 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 10 rev. 0.5, 2003-12 42 v ss 88 dq59 135 cb5 181 sa0 43 a1 89 v ss 136 v ddq 182 sa1 44 cb0 90 nc 137 ck0 183 sa2 45 cb1 91 sda 138 ck0 184 v ddspd 46 v dd 92 scl 139 v ss ?? 47 dqs8 93 v ss 140 dqs17 ? ? 1) a12 is used for 256mbit and 512mbit based modules only. table 5 address format density organization memory ranks sdrams # of sdrams # of row/bank/ column bits refresh period interval 1 gb 128m x 72 1 128m 4 18 13/2/12 8k 64 ms 7.8 s 1 gb 128m x 72 2 64m 8 18 13/2/11 8k 64 ms 7.8 s 2 gb 256m x 72 2 128m 4 36 13/2/12 8k 64 ms 7.8 s table 4 pin configuration 1) (cont?d) pin# symbol pin# symbol pin# symbol pin# symbol
data sheet 11 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 11 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module figure 1 block diagram: 1 rank 128m 72 ddr sdram dimm hys72d12 8[300/500]gbr?[5/6/7/7f]?b rs 0 dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cb0 cb1 cb2 cb3 dqs d8 cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 s s s s s s s s s s s s s s s s s s vss dqs1 dqs3 dqs8 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 dm8/dqs17 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. address and control resistors should be 22 ohms. 6. a13 is not wired for raw card b. v dd v ss d0-d17 d0-d17 v ddq d0-d17 d0-d17 vref v ddid strap: see note 4 ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a13 6 ra0-ra13 6 -> a0-a13 6 : sdrams d0-d17 ras rras -> ras : sdrams d0-d17 s 0 rs 0 -> cs : sdrams d0-d17 cas rcas -> cas : sdrams d0-d17 cke0 rcke0a -> cke: sdrams d0-d17 we rwe -> we : sdrams d0-d17 r e g i s t e r pck pck reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 v ddspd serial pd a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp
data sheet 12 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 12 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module figure 2 block diagram ? 2 ranks 64m 72 ddr sdram hys72d128321gbr-[5/6/7]?b dm0/dqs9 dqs3 dqs7 dqs2 dqs6 dqs1 dqs5 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm d9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm d10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm d11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm d12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm d13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm d14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dm d15 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm d16 rs 0 rs 1 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs dqs dqs dqs dqs dqs dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 dm d17 cs cs dqs8 dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs v dd v ss d0-d17 d0-d17 v ddq d0-d17 d0-d17 vref notes: 1 . dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. rs 0 and rs 1 alternate between the back and front sides of the dimm. 6. address and control resistors should be 22 ohms. 7. a13 is not wired for raw card a. v ddid strap: see note 4 ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams s 1 rs 1 -> cs : sdrams d9-d17 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a13 7 ra0-ra13 7 -> a0-a13 7 : sdrams d0-d17 ras rras -> ras : sdrams d0-d17 s 0 rs 0 -> cs : sdrams d0-d8 cas rcas -> cas : sdrams d0-d17 cke0 rcke0 -> cke: sdrams d0-d8 we rwe -> we : sdrams d0-d17 r e g i s t e r pck pck reset dm1/dqs10 dm2/dqs11 dm3/dqs12 dm4/dqs13 dm5/dqs14 dm7 dm6/dqs15 dm8/dqs17 dqs16 cke1 rcke1 -> cke: sdrams d9-d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ddspd serial pd a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp
data sheet 13 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module pin configuration data sheet 13 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module figure 3 block diagram ? 2 ranks 128m 72 ddr sdram hys72d 256320gbr-[5/6/7]?b pck pck rs 0 dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 ck0, ck 0 --------- pll* cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs s 1 rs 1 -> cs : sdrams d18-d35 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d35 a0-a13 ra0-ra13 -> a0-a13: sdrams d0- d35 ras rras -> ras : sdrams d0-d35 s 0 rso -> cs : sdrams d0-d17 v ss dqs1 dqs3 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 * wire per clock loading table/wiring diagrams v dd v ss d0-d35 d0-d35 v ddq d0-d35 d0-d35 vref rs 1 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. address and control resistors should be 22 ohms. 6. each chip select and cke pair alternate between decks for ther- mal enhancement. v ddid strap: see note 4 cas rcas -> cas : sdrams d0-d35 cke0 rcke0 -> cke: sdrams d0-d17 we rwe -> we : sdrams d0-d35 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d18 dqs dqs dqs dqs dqs dqs d19 d20 d21 d22 d23 d25 dqs d24 cs cs cs cs cs cs cs cs dm dm dm dm dm dm dm dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 d29 d30 d31 d32 d34 dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 cs cs cs cs cs cs cs cs dm dm dm dm dm dm dm dm cb0 cb1 cb2 cb3 dqs d8 cs dm dqs8 dqs d26 cs dm cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs dm dm8/dqs17 dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 cs dm reset cke1 rcke1 -> cke: sdrams d18-d35 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 v ddspd serial pd a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 14 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 14 rev. 0.5, 2003-12 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occu r if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 8) input different ial voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7)
data sheet 15 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 15 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied dire ctly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between th e input level on ck and the input level on ck . 7) the ratio of the pull-up current to the pull-down current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source volt age from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 7 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 16 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 16 rev. 0.5, 2003-12 table 8 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs chan ging once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; powe r-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
data sheet 17 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 17 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module table 9 i dd specification for ?7 part number & organization hys72d128500hr?7f?b hys72d128500hr?7?b hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256320gbr?7?b unit note 1)2) 1) dram component currents only 2) test condition fo r maximum values: v dd =2.7v, t a =10c 1 gb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?7f ?7 ?7 ?7 symbol typ. max. typ. max. typ. max. typ. max. i dd0 2158 2452 2028 2298 1587 1776 2586 2964 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of component s of rank 1 and 2; n =0 for 1 rank modules i dd1 2354 2746 2208 2568 1677 1911 2766 3234 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 430 448 430 448 430 448 484 520ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 736 808 736 808 736 808 1096 1240 ma 5) i dd2q 646 754 646 754 646 754 916 1132 ma 5) i dd3p 538 610 538 610 538 610 700 844ma 5) i dd3n 934 1042 934 1042 934 1042 1492 1708 ma 5) i dd4r 2179 2460 2118 2388 1632 1821 2676 3054 ma 3)4) i dd4w 2273 2554 2208 2478 1677 1866 2766 3144 ma 3) i dd5 4499 5263 4278 4998 2712 3126 4836 5664 ma 3) i dd6 414 468 414 468 414 468 451 560ma 5) i dd7 5493 6376 5088 5898 3117 3576 5646 6564 ma 3)4)
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 18 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 18 rev. 0.5, 2003-12 table 10 i dd specification for ?6 part number & organization hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b unit note 1)2) 1) dram component currents only 2) test condition fo r maximum values: v dd =2.7v, t a =10c 1gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. i dd0 2350 2710 1873 2116 3016 3502 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 2620 2980 2008 2251 3286 3772 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 484 502 484 502 538 574 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 880 970 880 970 1330 1510 ma 5) i dd2q 736 862 736 862 1042 1294 ma 5) i dd3p 628 700 628 700 826 970 ma 5) i dd3n 1096 1222 1096 1222 1762 2014 ma 5) i dd4r 2620 2980 2008 2251 3286 3772 ma 3)4) i dd4w 2710 3070 2053 2296 3376 3862 ma 3) i dd5 4690 5500 3043 3511 5356 6292 ma 3) i dd6 475 523.6 475 523.6 520 617.2 ma 5) i dd7 6310 7300 3853 4411 6976 8092 ma 3)4)
data sheet 19 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 19 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module table 11 i dd specification for ?5 part number & organization hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256320gbr?5?b unit note 1)2) 1) dram component currents only 2) test condition fo r maximum values: v dd =2.7v, t a =10c 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. i dd0 2680 3040 3436 3940 3436 3940 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 2950 3400 3706 4300 3706 4300 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 698 734 752 824 752 824 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 1184 1292 1724 1940 1724 1940 ma 5) i dd2q 986 1112 1328 1580 1328 1580 ma 5) i dd3p 860 932 1076 1220 1076 1220 ma 5) i dd3n 1400 1544 2156 2444 2156 2444 ma 5) i dd4r 3040 3490 3796 4390 3796 4390 ma 3)4) i dd4w 3130 3580 3886 4480 3886 4480 ma 3) i dd5 5290 6190 6046 7090 6046 7090 ma 3) i dd6 696.2 737.6 748.4 831.2 748.4 831.2 ma 5) i dd7 7090 8260 7846 9160 7846 9160 ma 3)4)
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 20 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 20 rev. 0.5, 2003-12 table 12 ac timing - absolute specifications ?6/?5 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.6 +0.6 ?0.7 +0.7 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.5 +0.5 ?0.6 +0.6 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 5 12 ? ? ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.6 +0.6 ?0.7 +0.7 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.6 +0.6 ?0.7 +0.7 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) ? +0.40 ? +0.45 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) ? +0.50 ? +0.55 ns tsopii 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2? t ck 2)3)4)5) write preamble setup time t wpres 0? 0? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 21 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 21 rev. 0.5, 2003-12 active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 65 ? 72 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) active to autoprecharge delay t rap 15 ? 18 ? ns 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)11) internal write to read command delay t wtr 1? 1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as m easured at the timing reference point indi cated in ac characteristics (note 3) is v tt . 6) these parameters guarantee devi ce timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same acce ss time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) the specific requirement is t hat dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning fr om hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for th is parameter, but system performance (bus turnar ound) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 12 ac timing - absolute specifications ?6/?5 (cont?d) parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 22 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 22 rev. 0.5, 2003-12 table 13 ac timing - absolute specifications ?7/?7f parameter symbol ?7f ?7 unit note/ test condition 1)1) ddr266 ddr266a min. max. min. max. dq output access time from ck/ck t ac ?0.75 +0.75 ?0.75 +0.75 ns 2)2)3)3)4)4)5)5) dqs output access time from ck/ck t dqsck ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 7.5 12 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.5 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.5 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.5 ? +0.5 ns tfbga 2)3)4)5) ? +0.5 ? +0.5 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.75 ? +0.75 ns tfbga 2)3)4)5) ? +0.75 ? +0.75 ns tsopii 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2? t ck 2)3)4)5) write preamble setup time t wpres 0? 0? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 0.9 ? 0.9 ? ns slow slew rate 3)4)5)6)10)
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 23 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 23 rev. 0.5, 2003-12 address and control input hold time t ih 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.0 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 45 120e+3 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 65 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 75 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? 20 ? ns 2)3)4)5) precharge command period t rp 20 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap 20 ? 20 ? ns 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)11) internal write to read command delay t wtr 1? 1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as m easured at the timing reference point indi cated in ac characteristics (note 3) is v tt . 6) these parameters guarantee devi ce timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same acce ss time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) the specific requirement is t hat dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning fr om hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for th is parameter, but system performance (bus turnar ound) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . table 13 ac timing - absolute specifications ?7/?7f parameter symbol ?7f ?7 unit note/ test condition 1)1) ddr266 ddr266a min. max. min. max.
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module electrical characteristics data sheet 24 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 24 rev. 0.5, 2003-12 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device.
data sheet 25 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 25 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 4spd contents table 14 spd codes for hys72d[128/256][300/321/320]gbr?5?b part number & organization hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256320gbr?5?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?5 ?5 ?5 label code pc3200r?30331 pc3200r?30331 pc3200r?30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex 0 programmed spd bytes in e2prom 80 80 80 1 total number of bytes in e2prom 08 08 08 2 memory type (ddr = 07h) 07 07 07 3 number of row addresses 0d 0d 0d 4 number of column addresses 0c 0b 0c 5 number of dimm ranks 01 02 02 6 data width (lsb) 48 48 48 7 data width (msb) 00 00 00 8 interface voltage levels 04 04 04 9 tck @ clmax (byte 18) [ns] 50 50 50 10 tac sdram @ clmax (byte 18) [ns] 50 50 50 11 error correction support (non- / ecc) 02 02 02 12 refresh rate 82 82 82 13 primary sdram width 04 08 04 14 error checking sdram width 04 08 04 15 tccd [cycles] 01 01 01 16 burst length supported 0e 0e 0e 17 number of banks on sdram device 04 04 04 18 cas latency 1c 1c 1c 19 cs latency 01 01 01 20 write latency 02 02 02 21 dimm attributes 26 26 26 22 component attributes c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 60 60 60 24 tac sdram @ clmax -0.5 [ns] 50 50 50 25 tck @ clmax -1 (byte 18) [ns] 75 75 75
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 26 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 26 rev. 0.5, 2003-12 26 tac sdram @ clmax -1 [ns] 50 50 50 27 trpmin [ns] 3c 3c 3c 28 trrdmin [ns] 28 28 28 29 trcdmin [ns] 3c 3c 3c 30 trasmin [ns] 28 28 28 31 module density per rank 01 80 01 32 tas, tcs [ns] 60 60 60 33 tah, tch [ns] 60 60 60 34 tds [ns] 40 40 40 35 tdh [ns] 40 40 40 36 ? 40 not used 00 00 00 41 trcmin [ns] 37 37 37 42 trfcmin [ns] 41 41 41 43 tckmax [ns] 28 28 28 44 tdqsqmax [ns] 28 28 28 45 tqhsmax [ns] 50 50 50 46 not used 00 00 00 47 dimm pcb height 01 01 01 48 ? 61 not used 00 00 00 62 spd revision 10 10 10 63 checksum of byte 0-62 e1 68 e2 64 jedec id code of infineon (1) c1 c1 c1 65 ? 71 jedec id code of infineon (2) 00 00 00 72 module manufacturer location xx xx xx 73 part number, char 1 37 37 37 74 part number, char 2 32 32 32 75 part number, char 3 44 44 44 table 14 spd codes for hys72d[128/256][300/321/320]gbr?5?b part number & organization hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256320gbr?5?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?5 ?5 ?5 label code pc3200r?30331 pc3200r?30331 pc3200r?30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
data sheet 27 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 27 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 76 part number, char 4 31 31 32 77 part number, char 5 32 32 35 78 part number, char 6 38 38 36 79 part number, char 7 33 33 33 80 part number, char 8 30 32 32 81 part number, char 9 30 31 30 82 part number, char 10 47 47 47 83 part number, char 11 42 42 42 84 part number, char 12 52 52 52 85 part number, char 13 35 35 35 86 part number, char 14 42 42 42 87 part number, char 15 20 20 20 88 part number, char 16 20 20 20 89 part number, char 17 20 20 20 90 part number, char 18 20 20 20 91 module revision code xx xx xx 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 ? 98 module serial number (1 - 4) xx xx xx 99 ? 127 not used 00 00 00 table 14 spd codes for hys72d[128/256][300/321/320]gbr?5?b part number & organization hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256320gbr?5?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?5 ?5 ?5 label code pc3200r?30331 pc3200r?30331 pc3200r?30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 28 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 28 rev. 0.5, 2003-12 table 15 spd codes for hys72d[128/256][300/321/320]gbr?6?b part number & organization hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?6 ?6 ?6 label code pc2700r?25330 pc2700r?25330 pc2700r?25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex 0 programmed spd bytes in e2prom 80 80 80 1 total number of bytes in e2prom 08 08 08 2 memory type (ddr = 07h) 07 07 07 3 number of row addresses 0d 0d 0d 4 number of column addresses 0c 0b 0c 5 number of dimm ranks 01 02 02 6 data width (lsb) 48 48 48 7 data width (msb) 00 00 00 8 interface voltage levels 04 04 04 9 tck @ clmax (byte 18) [ns] 60 60 60 10 tac sdram @ clmax (byte 18) [ns] 70 70 70 11 error correction support (non- / ecc) 02 02 02 12 refresh rate 82 82 82 13 primary sdram width 04 08 04 14 error checking sdram width 04 08 04 15 tccd [cycles] 01 01 01 16 burst length supported 0e 0e 0e 17 number of banks on sdram device 04 04 04 18 cas latency 0c 0c 0c 19 cs latency 01 01 01 20 write latency 02 02 02 21 dimm attributes 26 26 26 22 component attributes c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 75 24 tac sdram @ clmax -0.5 [ns] 70 70 70 25 tck @ clmax -1 (byte 18) [ns] 00 00 00
data sheet 29 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 29 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 26 tac sdram @ clmax -1 [ns] 00 00 00 27 trpmin [ns] 48 48 48 28 trrdmin [ns] 30 30 30 29 trcdmin [ns] 48 48 48 30 trasmin [ns] 2a 2a 2a 31 module density per rank 01 80 01 32 tas, tcs [ns] 75 75 75 33 tah, tch [ns] 75 75 75 34 tds [ns] 45 45 45 35 tdh [ns] 45 45 45 36 ? 40 not used 00 00 00 41 trcmin [ns] 3c 3c 3c 42 trfcmin [ns] 48 48 48 43 tckmax [ns] 30 30 30 44 tdqsqmax [ns] 28 28 28 45 tqhsmax [ns] 50 50 50 46 not used 00 00 00 47 dimm pcb height 00 00 00 48 ? 61 not used 00 00 00 62 spd revision 00 00 00 63 checksum of byte 0-62 ca 51 cb 64 jedec id code of infineon (1) c1 c1 c1 65 ? 71 jedec id code of infineon (2 - 8) 00 00 00 72 module manufacturer location xx xx xx 73 part number, char 1 37 37 37 74 part number, char 2 32 32 32 75 part number, char 3 44 44 44 table 15 spd codes for hys72d[128/256][300/321/320]gbr?6?b part number & organization hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?6 ?6 ?6 label code pc2700r?25330 pc2700r?25330 pc2700r?25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 30 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 30 rev. 0.5, 2003-12 76 part number, char 4 31 31 32 77 part number, char 5 32 32 35 78 part number, char 6 38 38 36 79 part number, char 7 33 33 33 80 part number, char 8 30 32 32 81 part number, char 9 30 31 30 82 part number, char 10 47 47 47 83 part number, char 11 42 42 42 84 part number, char 12 52 52 52 85 part number, char 13 36 36 36 86 part number, char 14 42 42 42 87 part number, char 15 20 20 20 88 part number, char 16 20 20 20 89 part number, char 17 20 20 20 90 part number, char 18 20 20 20 91 module revision code xx xx xx 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 ? 98 module serial number (1 - 4) xx xx xx 99 ? 127 not used 00 00 00 table 15 spd codes for hys72d[128/256][300/321/320]gbr?6?b part number & organization hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?6 ?6 ?6 label code pc2700r?25330 pc2700r?25330 pc2700r?25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex
data sheet 31 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 31 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module table 16 spd codes for hys72d[128/256][300/321/320]gbr?7?b part number & organization hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256320gbr?7?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks reg reg reg label code pc2100r?20330 pc2100r?20330 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex 0 programmed spd bytes in e2prom 80 80 80 1 total number of bytes in e2prom 08 08 08 2 memory type (ddr = 07h) 07 07 07 3 number of row addresses 0d 0d 0d 4 number of column addresses 0c 0b 0c 5 number of dimm ranks 01 02 02 6 data width (lsb) 48 48 48 7 data width (msb) 00 00 00 8 interface voltage levels 04 04 04 9 tck @ clmax (byte 18) [ns] 70 70 70 10 tac sdram @ clmax (byte 18) [ns] 75 75 75 11 error correction support (non- / ecc) 02 02 02 12 refresh rate 82 82 82 13 primary sdram width 04 08 04 14 error checking sdram width 04 08 04 15 tccd [cycles] 01 01 01 16 burst length supported 0e 0e 0e 17 number of banks on sdram device 04 04 04 18 cas latency 0c 0c 0c 19 cs latency 01 01 01 20 write latency 02 02 02 21 dimm attributes 26 26 26 22 component attributes c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 75 24 tac sdram @ clmax -0.5 [ns] 75 75 75 25 tck @ clmax -1 (byte 18) [ns] 00 00 00
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 32 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 32 rev. 0.5, 2003-12 26 tac sdram @ clmax -1 [ns] 00 00 00 27 trpmin [ns] 50 50 50 28 trrdmin [ns] 3c 3c 3c 29 trcdmin [ns] 50 50 50 30 trasmin [ns] 2d 2d 2d 31 module density per rank 01 80 01 32 tas, tcs [ns] 90 90 90 33 tah, tch [ns] 90 90 90 34 tds [ns] 50 50 50 35 tdh [ns] 50 50 50 36 ? 40 not used 00 00 00 41 trcmin [ns] 41 41 41 42 trfcmin [ns] 4b 4b 4b 43 tckmax [ns] 30 30 30 44 tdqsqmax [ns] 32 32 32 45 tqhsmax [ns] 75 75 75 46 not used 00 00 00 47 dimm pcb height 00 00 00 48 ? 61 not used 00 00 00 62 spd revision 00 00 00 63 checksum of byte 0-62 86 0d 87 64 jedec id code of infineon (1) c1 c1 c1 65 ? 71 jedec id code of infineon (2 - 8) 00 00 00 72 module manufacturer location xx xx xx 73 part number, char 1 37 37 37 74 part number, char 2 32 32 32 75 part number, char 3 44 44 44 table 16 spd codes for hys72d[128/256][300/321/320]gbr?7?b part number & organization hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256320gbr?7?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks reg reg reg label code pc2100r?20330 pc2100r?20330 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex
data sheet 33 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 33 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 76 part number, char 4 31 31 32 77 part number, char 5 32 32 35 78 part number, char 6 38 38 36 79 part number, char 7 33 33 33 80 part number, char 8 30 32 32 81 part number, char 9 30 31 30 82 part number, char 10 47 47 47 83 part number, char 11 42 42 42 84 part number, char 12 52 52 52 85 part number, char 13 37 37 37 86 part number, char 14 42 42 42 87 part number, char 15 20 20 20 88 part number, char 16 20 20 20 89 part number, char 17 20 20 20 90 part number, char 18 20 20 20 91 module revision code xx xx xx 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 ? 98 module serial number (1 - 4) xx xx xx 99 ? 127 not used 00 00 00 table 16 spd codes for hys72d[128/256][300/321/320]gbr?7?b part number & organization hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256320gbr?7?b 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks reg reg reg label code pc2100r?20330 pc2100r?20330 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 34 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 34 rev. 0.5, 2003-12 table 17 spd codes for hys72d128500hr?[7f/7]?b part number & organization hys72d128500hr?7f?b hys72d128500hr?7?b 1 gb 1 gb 72 72 1 rank 1 rank reg reg label code pc2100r?20220 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex 0 programmed spd bytes in e2prom 80 80 1 total number of bytes in e2prom 08 08 2 memory type (ddr = 07h) 07 07 3 number of row addresses 0d 0d 4 number of column addresses 0c 0c 5 number of dimm ranks 01 01 6 data width (lsb) 48 48 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 tck @ clmax (byte 18) [ns] 70 70 10 tac sdram @ clmax (byte 18) [ns] 75 75 11 error correction support (non- / ecc) 02 02 12 refresh rate 82 82 13 primary sdram width 04 04 14 error checking sdram width 04 04 15 tccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram device 04 04 18 cas latency 0c 0c 19 cs latency 01 01 20 write latency 02 02 21 dimm attributes 26 26 22 component attributes c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 24 tac sdram @ clmax -0.5 [ns] 75 75 25 tck @ clmax -1 (byte 18) [ns] 00 00
data sheet 35 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 35 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 26 tac sdram @ clmax -1 [ns] 00 00 27 trpmin [ns] 3c 50 28 trrdmin [ns] 3c 3c 29 trcdmin [ns] 3c 50 30 trasmin [ns] 2d 2d 31 module density per rank 01 01 32 tas, tcs [ns] 90 90 33 tah, tch [ns] 90 90 34 tds [ns] 50 50 35 tdh [ns] 50 50 36 ? 40 not used 00 00 41 trcmin [ns] 3c 41 42 trfcmin [ns] 4b 4b 43 tckmax [ns] 30 30 44 tdqsqmax [ns] 32 32 45 tqhsmax [ns] 75 75 46 not used 00 00 47 dimm pcb height 00 00 48 ? 61 not used 00 00 62 spd revision 00 00 63 checksum of byte 0-62 59 86 64 jedec id code of infineon (1) c1 c1 65 ? 71 jedec id code of infineon (2 ? 8) 00 00 72 module manufacturer location xx xx 73 part number, char 1 37 37 74 part number, char 2 32 32 75 part number, char 3 44 44 table 17 spd codes for hys72d128500hr?[7f/7]?b part number & organization hys72d128500hr?7f?b hys72d128500hr?7?b 1 gb 1 gb 72 72 1 rank 1 rank reg reg label code pc2100r?20220 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module spd contents data sheet 36 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 36 rev. 0.5, 2003-12 76 part number, char 4 31 31 77 part number, char 5 32 32 78 part number, char 6 38 38 79 part number, char 7 35 35 80 part number, char 8 30 30 81 part number, char 9 30 30 82 part number, char 10 48 48 83 part number, char 11 52 52 84 part number, char 12 37 37 85 part number, char 13 46 42 86 part number, char 14 42 20 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 91 module revision code xx xx 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 ? 98 module serial number (1 ? 4) xx xx 99 ? 127 not used 00 00 table 17 spd codes for hys72d128500hr?[7f/7]?b part number & organization hys72d128500hr?7f?b hys72d128500hr?7?b 1 gb 1 gb 72 72 1 rank 1 rank reg reg label code pc2100r?20220 pc2100r?20330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
data sheet 37 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module package outlines data sheet 37 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module 5 package outlines figure 4 package outline ? raw card c ddr re gistered dimm hys7 2d128300gbr?[5/6/7]?b 128.95 2.5 1 64.77 ?0.1 0.1 a bc 4 0.1 0.1 a 120.65 6.35 1.27 95 x = 2.175 49.53 a c b 133.35 92 b 0.13 28.58 0.15 b a c 0.13 0.05 1 1.27 0.1 ab c detail of contacts 0.2 2.5 0.2 3.8 93 1.8 0.1 c 0.1 ab 17.8 184 10 1.27 0.4 c 0.1 4 max. burr max. 0.4 allowed 3 min. 6.62 l-dim-184-22-2
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module package outlines data sheet 38 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 38 rev. 0.5, 2003-12 4 max. 1.27 c 0.1 0.4 0.1 ?0.1 0.1 2.5 0.1 4 1 x 95 c 64.77 ab 120.65 1.27 = 2.175 6.35 a b c a 133.35 128.95 49.53 92 0.15 c ab 0.13 b 28.58 b a 0.1 c 1.8 c 1 b 0.1 a detail of contacts 0.2 1.27 3.8 0.13 93 0.2 2.5 0.05 17.8 184 10 0.1 3 min. burr max. 0.4 allowed 6.62 figure 5 package outline ? raw card b ddr re gistered dimm hys7 2d128321hr?[5/6/7]?b l-dim-184-23-2
data sheet 39 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module package outlines data sheet 39 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module figure 6 package outline ? raw card d ddr re gistered dimm hys7 2d256320gbr?[5/6/7]?b 128.95 133.35 0.15 a bc a a 6.62 6.35 2.175 49.53 92 0.1 2.5 ?0.1 c ab 1 64.77 0.13 30.48 b 0.1 4 0.1 b a c 4 max. c 0.4 0.1 1.27 1.8 0.1 0.1 b ac 0.13 3.8 3 min. 17.8 10 93 184 burr max. 0.4 allowed detail of contacts 0.2 1.27 0.05 1 0.1 ab c 0.2 2.5 l-dim-184-25
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module package outlines data sheet 40 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module data sheet 40 rev. 0.5, 2003-12 1 92 a 93 184 128.95 a 0.1 a bc 133.35 4 max. 0.15 b a c 1.27 0.4 b c 0.13 30.48 0.1 6.35 0.1 2.5 64.77 ?0.1 abc 2.175 6.62 49.53 0.1 4 0.1 0.1 1.8 a c b 3.8 0.13 3 min. 17.8 10 1.27 1 0.05 a 0.1 c b detail of contacts 0.2 2.5 0.2 120.65 x 95 1.27 = 1) 1) burr max. 0.4 allowed 1) on ecc modules only figure 7 package outline ? raw card m ddr registered dimm hys72d128500hr?[7/7f]?b l-dim-184-12-3
data sheet 41 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module application note data sheet 41 rev. 0.5, 2003-12 6 application note power up and power management on ddr registered dimms (according to jedec ballot jc-42.5 item 1173) 184-pin double data rate (ddr) registered dimms include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. one feature is externally controlled via a system- generated reset signal ; the second is based on m odule detectio n of the input clocks. these enhancements permit the modules to power up with sdram outputs in a hi gh-z state (eliminating risk of high current dissipations and/or dotted i/os), and result in the powering-down of module support devices (registers and phase-locked loop) when the memory is in self-refresh mode. the new reset pin controls power diss ipation on the module?s registers a nd ensures t hat cke and other sdram inputs are maintained at a va lid ?low? level during powe r-up and self refresh. when reset is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register po wer consumption. the reset pin, located on dimm tab #10, is driven from the system as an asynchronous signal according to the attached details . using this function also permits the system and dimm clocks to be stopped during memory self refresh operation, while ensuring that the sdrams stay in self refresh mode. as described in the table above, a low on the reset input ensures that the clock enable (cke) signal(s) are maintained low at the sdram pins (cke being one of the 'q' signals at the register output). holding cke low maintains a high impedance state on the sdram dq, dqs and dm outputs ? wher e they will remain until activated by a valid ?read? cycle. cke low also main tains sdrams in self refr esh mode when applicable. the ddr pll devices automatically detect clock activity above 20mhz. when an input clock frequency of 20mhz or greater is detected, the pll begins operation and initiates clock frequency lock (the minimum operating frequency at which all specif ications will be met is 95mhz). if the cloc k input frequency drop s below 20mhz (actual detect frequency will vary by vendor), the pll vco (voltage controlled oscillator) is stoppe d, outputs are made high-z, and the differential inputs are powered down ? resulting in a total pll current consumption of less than 1ma. use of this low power pll function makes the use of the pll reset (or g pin) unnecessary, and it is tied inactive on the dimm. this application note descr ibes the required and optional system se quences associated with the ddr registered dimm 'reset ' function. it is important to note that all references to cke refer to both cke0 and cke1 for a 2- bank dimm. because reset applies to all dimm register devices, it is therefore not possible to uniquely control cke to one physical dimm bank through the us e of the reset pin. table 18 the function for reset is as follows: 1) 1) x : don?t care, hi-z : high impedance, qo: data latched at the previous of ck risning and ck falling register inputs register outputs reset ck ck data in (d) data out (q) h rising falling h h h rising falling l l h l or h l or h x qo h high z high z x illegal input conditions l x or hi-z x or hi-z x or hi-z l
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module application note data sheet 42 rev. 0.5, 2003-12 data sheet 42 rev. 0.5, 2003-12 power-up sequence with reset ? required 1. the system sets reset at a valid low level. this is the preferred default state during power-up. this input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that cke is at a stable low-level at the ddr sdrams. 2. the power supplies should be init ialized according to the jedec-appr oved initialization sequence for ddr sdrams. 3. stabilization of clocks to the sdra m the system must drive clocks to the applicatio n frequency (pll operation is not assured until the input clock reaches 20mhz). stab ility of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, th e required pll stabilization ti me (assuming power to the dimm is stable) is 100 microseconds. when a stable clock is present at the sdram input (driven from the pll), the ddr sdram requires 200 sec prior to sdram operation. 4. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the jedec initialization sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 5. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to re ceive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 7. the system can begin the jedec-defined ddr sdram power-up sequence (according to the jedec- pproved initialization sequence). self refresh entry (reset low, clocks powered off) ? optional self refresh can be used to retain data in ddr sdram dimms even if the rest of the system is powered down and the clocks are off. this mode allows the ddr sdrams on the dimm to retain data without external clocking. self refresh mode is an id eal time to utilize the reset pin, as this can reduce register power consumption (reset low deactivates register ck and ck, data input receivers, and data output drivers). 1. the system applies self re fresh entry command. (cke low, cs low, ras low, cas low, we high) note: note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that cke, and all other control and address si gnals, are a stable low-level at the ddr sdrams. since the reset signal is asynchronous, setting the reset timing in relation to a specif ic clock edge is not required. 3. the system turns off clock inputs to the dimm. (optional) a. in order to reduce dimm pll current, the clock inputs to the dimm are turned off, resulting in high-z clock inputs to both the sdrams and the registers. this must be done after the reset deactivate time of the register (t (inact) ) . the deactivate time defines the time in which the clocks and the control and address
data sheet 43 rev. 0.5, 2003-12 hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module application note data sheet 43 rev. 0.5, 2003-12 signals must maintain valid levels after reset low has been applied and is sp ecified in the register and dimm documentation. b. the system may release dimm a ddress and control inputs to high-z. this can be done after the reset deactivate time of the register. the deactivate time de fines the time in which the clocks and the control and the address signals must ma intain valid levels after r eset low has been applied. it is highly recommended that cke continue to remain lo w during this operation. 4. the dimm is in lowest power self refresh mode. self refresh exit (reset low, clocks powered off) ? optional 1. stabilization of clocks to the sdram. the system mu st drive clocks to the application frequency (pll operation is not assu red until the input clock reaches ~20mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, th e required pll stabilization ti me (assuming power to the dimm is stable) is 100 microseconds. 2. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the jedec self refresh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receive commands. since the reset signal is as ynchronous, reset timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 2. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 5. system can begin the jedec-defined ddr sdram self refresh exit procedure. self refresh entry (reset low, clocks running) ? optional although keeping the clocks running increases power consumption from the on-dimm pll during self refresh, this is an alternate operating mode for these dimms. 1. system enters self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares ? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that cke is a stable low-level at the ddr sdrams. 3. the system may release dimm addr ess and control inputs to high-z. this can be done after the reset deactivate time of the register (t (inact) ). the deacti vate time describes the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during the operation. 4. the dimm is in a low power, self refresh mode.
hys72d[128/256][ 300/320/321/500][gbr/hr ]-[5/6/7/7f]-b registered double data rate sdram module application note data sheet 44 rev. 0.5, 2003-12 data sheet 44 rev. 0.5, 2003-12 self refresh exit (reset low, clocks running) ? optional 1. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command de fined by the self refresh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. the system switches reset to a logic 'high' level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 1. it is also a functional requirement that the registers maintain a low state at the cke outputs in order to guarantee that the ddr sdrams continue to receive a low level on cke. this activation time, from asynchronous switching of reset from low to high, until the registers are stable and ready to accept an input signal, is t (act ) as specified in the register and dimm documentation. 4. the system can begin jedec defined ddr sdram self refresh exit procedure. self refresh entry/exit (reset high, clocks running) ? optional as this sequence does not involve the use of the reset function, the jedec standard sdram specification explains in detail the method for entering and exiting self refresh for this case. self refresh entry (reset high, clocks powered off) ? not permissible in order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on cke, or the clocks are powered off and reset is asserted low according to the sequence defined in this application note . in the case where reset remains high and the clocks are powered off, the pll drives a high-z clock input into the register clock input. without the low level on reset an unknown dimm state will result.
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